This position will be responsible for architecting and supporting DFT for our next generation of IoT products. You are an experienced user of DFT/ATPG/MBIST tools and can apply them to SOCs. You are very innovative at integrating DFT efficiently given power, multi-clock and other design constraints. You have experience with post-silicon bringup, debug and manufacturing test. This position can be based in San Diego, Irvine, or San Jose, preferably in San Diego, CA.

Key Responsibilities

• DFT Architect for IoT SOC Devices
• Run ATPG/DFT/MBIST tools at subsystem and Top Levels
• Assemble a DFT plan that assists bringup and guarantees quality in manufacturing test
• Understand debug, trace, and other isolation techniques
• Run ATPG and other vector generation
• Support the design team in debugging and meet low power and other constraints
• Verify your work effectively

• Deep knowledge of Mentor Tessent or equivalent DFT/test tools
• Verification of integrated DFT/1149.1/1149.5
• Hands-on experience with scripting in Python/TCL
• Experience with SOC development and DFT integration
• Working knowledge of IC management revision control
• Experience with Device bringup and diagnosis
• Development and debug of manufacturing test
• Excellent verbal and written communication skills
• Team player with a passion for quality and a strong sense of urgency and pride in their work
• Innovative to meet unique device constraints
• DFT background
• Wifi experience
• Worked with Mentor Tessent Tool
• Post-silicon hands-on experience